Integrated circuits often require high voltage transistors in addition to low voltage transistors. The addition of high voltage transistors may significantly increase manufacturing cost by adding a second thicker gate dielectric to support a higher voltage and by adding additional photoresist patterns and implants for high voltage wells and source and drain extensions.
One method to avoid some of the cost of adding high voltage transistors to a baseline CMOS process flow is to construct drain extended MOS transistors (DEMOS). DEMOS transistors eliminate the need add a second, thicker gate dielectric to support the high voltage by building a depleted drift region in series with the drain of a low voltage transistor gate so that sufficient voltage is dropped across the drift region to protect the low voltage gate dielectric. This enables a low voltage transistor gate to reliably switch high voltage without damage to the low voltage gate dielectric.
The conventional method for adding DENMOS transistors to a baseline CMOS process flow is to add a deep n-well pattern and deep n-well implant. A p-well is formed in the deep n-well. The DENMOS gate is formed over a p-well, n-well boundary and the drain contact is located in the n-well some distance from the gate. The n-well between the DENMOS gate and the drain contact forms the drift region of the DENMOS transistor.